1. Field of the Invention
The present invention is related to the field of computer systems. More particularly, the present invention is a method and apparatus for providing non-atomic level parity protection for storing data in a random access memory.
2. Art Background
Traditionally, the smallest amount of data stored in the random access memory (RAM) 16 that can be manipulated directly by the central processing unit (CPU) (not shown) of a computer system 10, is a byte, i.e. eight bits, 22a, 22b, 22c or 22d (FIG. 1a), even though there are machine instructions available for a programmer to read or write in bytes, half-words, i.e. two bytes, full-words, i.e. four bytes, or double-words, i.e. eight bytes. That is why, typically parity protection provided for storing data in the RAM 16 is provided at this atomic level, i.e. the byte level. An additional ninth bit, 24a, 24b, 24c, or 24d is provided for every byte 22a, 22b, 22c, or 22d, to be used as the parity bit. Thus, for a "thirty-two bit computer system", the data path 18 between the RAM 16 and the RAM controller 14 is typical thirty-six bits, even though the four parity bits 24a, 24b, 24c, or 24d are not accessible to the user.
The parity bit of each byte is set or reset by the random access memory controller during each write operation. Typically the RAM controller receives the data from the CPU, block 32 (FIG. 1b). The RAM controller determines which byte or bytes need to be written, block 34. The RAM controller then generates the corresponding parity bits for the bytes to be written, block 36. Each parity bit is set or reset so that the total number of 1 bits for each byte is always odd or even, depending on whether odd parity or even parity is used by the computer system. After generating the parity bits, the RAM controller writes the appropriate byte or bytes into the RAM along with their parity bits, block 38.
The parity bit in turn is checked by the RAM controller during each read operation. Typically, the RAM controller retrieves the whole word from the RAM, block 42 (FIG. 1c). The RAM controller determines which byte or bytes are being fetched 44 and returns only what is needed to the CPU 46. At the same time, the RAM controller checks the parity bit of each byte being returned for error 48, and reports the parity error to the CPU 49 if detected.
The traditional way of providing parity protection is costly, particularly in terms of hardware space for microcomputers. One ninth of the random access memory is used for parity protection. As will be discussed, the present invention overcomes the disadvantage of the prior art and provides a method and apparatus for providing non-atomic level parity protection for storing data in random access memory.